The present invention relates to semiconductor device fabrication, and more particularly to a method of forming a junction on insulator (JOI) structure which has low junction leakage, reduced junction capacitance, and substantially little or no floating body effects which, if present, may degrade the stability and/or threshold voltage of the semiconductor device. The inventive method does not include the use of a silicon-on-insulator (SOI) substrate; instead a bulk semiconductor substrate is employed.
A significant fraction of the total power consumption in low-power bulk complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) and other devices is attributed to the junction leakage in the array which occurs during standby, i.e., when the device is not actively in operation. In typical low-power applications, the active duty factor is less than 1%. This results injunction leakage during standby contributing significantly to the total power. It is therefore necessary to find a means of reducing junction leakage in low-power bulk CMOS SRAMs.
Another problem facing many bulk semiconductor devices is performance degradation which is caused by high source/drain junction capacitance. Reduction in source/drain junction capacitance is thus required in many applications for improved performance.
It is known in the semiconductor industry that a junction on insulator structure allows for both source/drain junction leakage and capacitance to be reduced. Most of the commonly available junction on insulator structures are formed using a silicon-on-insulator (SOI) which includes a buried oxide layer that electrically isolates a top Si-containing layer from a bottom Si-containing substrate layer. A major drawback in forming junction on insulator structures on an SOI is that costly processing steps are required, particularly for the fabrication of the SOI substrate material itself. Moreover, SOI materials are highly susceptible to floating body effects which greatly limit the stability and threshold voltage of the overall device.
Another problem of using SOI materials in forming JOI structures is that it is extremely difficult and, in some instances, nearly impossible to integrate a bulk semiconductor device with a structure containing an SOI material. Such bulk semiconductor devices may include vertical bipolar transistors which may require an SOI material that is considerably thicker than desired for SOI MOSFETs.
In view of the above drawbacks in the prior art, there is still a need for developing a new and improved method of forming a JOI structure on a surface of a bulk semiconductor substrate which has low junction leakage and reduced junction capacitance associated therewith.
One object of the present invention is to provide a method of forming a JOI structure on a bulk semiconductor substrate.
A further object of the present invention is to provide a method of forming a JOI structure in which standby power reduction caused by junction leakage is substantially reduced.
A yet further object of the present invention is to provide a method of forming a JOI structure having reduced junction capacitance.
A still further object of the present invention is to provide a method of forming a JOI structure which exhibits little or substantially no floating body effects.
An even further object of the present invention is to provide a method of forming a JOI structure using processing steps that are compatible with existing complementary metal oxide semiconductor (CMOS) processing steps, thereby not increasing the fabrication cost of the JOI structure.
These and other objects and advantages are achieved in the present invention by utilizing a method whereby an insulating layer such as an oxide is formed under the source/drain diffusion regions, but not under the channel region. The insulating layer is formed in the present invention after forming the gate stack region and recessing of the semiconductor surface surrounding the gate stack region. These steps of the present invention are followed by deposition of a conductive material and optional heavy source/drain diffusion formation. The optional heavy source/drain diffusion formation is required when the conductive material is polysilicon or amorphous Si, whereas it may be omitted when the conductive material is an elemental metal including alloys, nitrides, and silicides thereof.
Specifically, the method of the present invention comprises the steps of:
(a) selectively recessing portions of a semiconductor substrate that abut one or more gate stack regions, while not recessing other portions of said semiconductor substrate that contain well contacts;
(b) forming an insulating layer on at least said recessed portions of said semiconductor substrate;
(c) filling said recessed portions of said semiconductor substrate with a conductive material and planarizing to a top surface of said one or more gate stack regions;
(d) recessing a portion of said conductive material abutting said one or more gate stack regions, wherein said recessing stops above said insulating layer; and
(e) removing said insulating layer from over said well contacts.
When the conductive material employed in step (c) is polysilicon or amorphous Si, then the method of the present invention includes the step of: (f) forming heavy source/drain diffusion regions in said recessed portion of said polysilicon or amorphous Si.
In the present invention, the one or more gate stack regions include at least a gate conductor region, a dielectric capping layer that is formed above the gate conductor region and insulating spacers covering the vertical sidewalls of each gate conductor region. In accordance with the present invention, the dielectric capping layer is removed after step (e) above.
In another embodiment of the present invention, a sacrificial or disposable spacer is formed atop each sidewall spacer that is present on exposed vertical sidewalls of the gate stack region prior to performing step (a) above. The disposable spacers are removed after performing step (a). Note that the spacers covering the vertical sidewalls of the gate region are not removed in either embodiment of the present invention.